MPC7448 datasheet(21/60 Pages) FREESCALE

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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 3

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 7 provides the AC test load for TDO and the boundary-scan outputs of the MPC7448.

Figure 7. Alternate AC Test Load for the JTAG Interface

Figure 8 provides the JTAG clock input timing diagram.

Figure 8. JTAG Clock Input Timing Diagram

Input setup times:

Boundary-scan data

TMS, TDI

tDVJH

tIVJH

—

Input hold times:

Boundary-scan data

TMS, TDI

tDXJH

tIXJH

—

Valid times:

Boundary-scan data

TDO

tJLDV

tJLOV

Output hold times:

Boundary-scan data

TDO

tJLDX

tJLOX

—

TCK to output high impedance:

Boundary-scan data

TDO

tJLDZ

tJLOZ

4, 5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see Figure 7).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1 (continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

VM = Midpoint Voltage (OVDD/2)

tTCLK

tJR

tJF

tJHJL

TCLK

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