SP6136 datasheet(13/18 Pages) SIPEX

13 / 18 page

Oct 3-06 Rev L

SP636 Synchronous Buck Controller

ode has high forward voltage and reverse

recovery problems. The reverse recovery of

the body diode causes additional switching

noise when the diode turns off. The Schottky

diode alleviates these sources of noise and

additionally improves efficiency thanks to its

low forward voltage. The reverse voltage

across the diode is equal to input voltage,

and the diode must be able to handle the

peak current equal to the maximum load

current.

The power dissipation of the Schottky diode

is determined by:

PDIODE = 2 • VF • Iout • TNOL • FS

where:

TNOL = non-overlap time between GH and GL.

VF = forward voltage of the Schottky diode.

Loop Compensation Design

The open loop gain of the whole system can

be divided into the gain of the error ampli-

fier, PWM modulator, buck converter output

stage, and feedback resistor divider. In or-

der to cross over at the selected frequency

FCO

, the gain of the error amplifier has to

compensate for the attenuation caused by

the rest of the loop at this frequency.

The goal of loop compensation is to manipu-

late loop frequency response such that its

gain crosses over 0db at a slope of -20db/

dec. The first step of compensation design

is to pick the loop crossover frequency. High

crossover frequency is desirable for fast

transient response, but often jeopardizes

the system stability. Crossover frequency

should be higher than the ESR zero but

less than 1/5 of the switching frequency.

The ESR zero is contributed by the ESR

associated with the output capacitors and

can be determined by:

ƒz(Esr) =

π • Cout • REsr

The next step is to calculate the complex

conjugate poles contributed by the LC output

filter,

ƒp(Lc) =

π •

√L • Cout

When the output capacitors are of a Ceramic

Type,theSP6136EvaluationBoardrequires

a Type III compensation circuit to give a phase

boostof180°inordertocounteracttheeffects

of an under damped resonance of the output

filter at the double pole frequency.

APPLICATION INFORMATION

(SRz2Cz2+1)(SR1Cz3+1)

(SRESRCOUT+ 1)

[S2LC

OUT+S(RESR+RDC) COUT+1]

VIN

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

VRAMP_PP

VOUT

(Volts)

VREF

(Volts)

Notes: R

ESR = Output Capacitor Equivalent Series Resistance.

DC = Output Inductor DC Resistance.

RAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> R

ESR & RDC

VREF

(R1 + R2)

VOUT

VFBK

(Volts)

Type III Voltage Loop

Compensation

AMP (s) Gain Block

PWM Stage

PWM Gain

Block

Output Stage

OUT (s) Gain

Block

Voltage Feedback

FBK Gain Block

Figure 5: SP6136 Voltage Mode

Control Loop with Loop Dynamic

Definitions:

REsr

= Output Capacitor Equivalent Series Resistance

Rdc = Output Inductor DC Resistance

Vramp

_ pp = SP636 internal RAMP Amplitude Peak to Peak Voltage

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