ADM1176-2ARMZ-R7 datasheet(7/24 Pages) AD

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ADM1176

Rev. 0 | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

SENSE

GND

TIMER 5

GATE

SDA

SCL

ADM1176

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

VCC

Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage

lockout (UVLO) circuit resets the ADM1176 when a low supply voltage is detected.

SENSE

Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current

limit. The hot swap operation of the ADM1176 controls the external FET gate to maintain the (VVCC − VSENSE)

voltage at 100 mV or below.

Undervoltage Input Pin. Active-high pin. An internal ON comparator has a trip threshold of 1.3 V, and the

output of this comparator is used as an enable for the hot swap operation. With an external resistor divider

from VCC to GND, this pin can be used to enable the hot swap operation on a specific voltage on VCC, giving

an undervoltage function.

GND

Chip Ground Pin.

TIMER

Timer Pin. An external capacitor, CTIMER, sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.

The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection

with an external Zener can be used to force this pin high.

SCL

I2C Clock Pin. Open-drain input requires an external resistive pull-up.

SDA

I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.

I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen different

I2C address options are available, depending on the external configuration of the A0 pin and A1 pin.

I2C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor. Sixteen different

I2C address options are available, depending on the external configuration of the A0 pin and the A1 pin.

GATE

GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the

FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET

GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)

by modulating the GATE pin.

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