VIPER50SLASHSP datasheet(14/23 Pages) STMICROELECTRONICS

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VIPer50/SP - VIPer50A/ASP

TRANSCONDUCTANCE ERROR AMPLIFIER

The VIPer50/50A includes a transconductance

error amplifier. Transconductance Gm is the

change in output current (ICOMP) versus change in

input voltage (VDD). Thus:

The output impedance ZCOMP at the output of this

amplifier (COMP pin) can be defined as:

This last equation shows that the open loop gain

AVOL can be related to Gm and ZCOMP:

AVOL = Gm x ZCOMP

where Gm value for VIPer50/50A is 1.5 mA/V

typically.

Gmis well defined by specification, but ZCOMP and

therefore AVOL are subject to large tolerances. An

impedance Z can be connected between the

COMP pin and ground in order to define more

accurately the transfer function F of the error

amplifier, according to the following equation, very

similar to the one above:

F(S) = Gm x Z(S)

The error amplifier frequency response is reported

in figure 10 for different values of a simple

resistance connected on the COMP pin. The

unloaded transconductance error amplifier shows

an internal ZCOMP of about 330 KΩ. More complex

impedance can be connected on the COMP pin to

achieve different compensation laws. A capacitor

will provide an integrator function, thus eliminating

the DC static error, and a resistance in series

leads to a flat gain at higher frequency, insuring a

correct phase

margin. This

configuration is

illustrated in figure 18.

As shown in figure 18 an additional noise filtering

capacitor of 2.2 nF is generally needed to avoid

any high frequency interference.

It can also be interesting to implement a slope

compensation when working in continuous mode

with duty cycle higher than 50%. Figure 19 shows

such a configuration. Note that R1 and C2 build

the classical compensation network, and Q1 is

injecting the slope compensation with the correct

polarity from the oscillator sawtooth.

EXTERNAL CLOCK SYNCHRONIZATION

The

OSC

provides

synchronisation

capability,

when

connected

external

frequency source. Figure 20 shows one possible

schematic to be adapted depending on the

specific needs. If the proposed schematic is used,

the pulse duration must be kept at a low value

(500ns is sufficient) for minimizing consumption.

The optocoupler must be able to provide 20mA

through the optotransistor.

PRIMARY PEAK CURRENT LIMITATION

The primary IDPEAK current and, as resulting

effect, the output power can be limited using the

simple circuit shown in figure 21. The circuit based

on Q1, R1 and R2 clamps the voltage on the

∂I

COMP

∂V

------------------------

COMP

∂V

COMP

∂I

COMP

---------------------------

---------

∂V

COMP

∂V

---------------------------

Figure 16: Mixed Soft Start and Compensation

Figure 17: Latched Shut Down

13V

OSC

COMP SOURCE

DRAIN

VDD

VIPer50

+ C2

+ C3

AUXILIARY

WINDING

FC00331

13V

OSC

COMP

SOURCE

DRAIN

VDD

VIPer50

Shutdown

FC00340

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