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VIPER50A/ASP 数据表(PDF) 17 Page - STMicroelectronics |
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VIPER50A/ASP 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 23 page ![]() 17/23 VIPer50/SP - VIPer50A/ASP 1 Figure 23: Recommended Layout LAYOUT CONSIDERATIONS Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: - To minimize power loops: the way the switched power current must be carefully analyzed and the corresponding paths must present the smallest possible inner loop area. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. - To use different tracks for low level signals and power ones. The interferences due to a mixing of signal and power may result in instabilities and/or anomalous behavior of the device in case of violent power surge (Input overvoltages, output short circuits...). In case of VIPer, these rules apply as shown in figure 23. The loops C1-T1-U1, C5-D2-T1, C7-D1- T1 must be minimized. C6 must be as close as possible to T1. The signal components C2, ISO1, C3 and C4 use a dedicated track to be connected directly to the source of the device. T1 U1 VIPerXX0 13V OSC COMP SOURCE DRAIN VDD - + 1 5 2 3 4 C4 C2 C5 C1 D2 R1 R2 D1 C7 C6 C3 ISO1 A
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