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74LVC16601APVG 数据表(PDF) 1 Page - Renesas Technology Corp |
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74LVC16601APVG 数据表(HTML) 1 Page - Renesas Technology Corp |
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1 / 7 page ![]() INDUSTRIALTEMPERATURERANGE IDT74LVC16601A 3.3VCMOS18-BIT UNIVERSAL BUS TRANSCEIVER 1 SEPTEMBER 2015 INDUSTRIAL TEMPERATURE RANGE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. © 2015 Integrated Device Technology, Inc. DSC-4599/6 FEATURES: • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) •VCC = 3.3V ± 0.3V, Normal Range •VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4 μμμμμ W typ. static) • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP package FUNCTIONAL BLOCK DIAGRAM APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise IDT74LVC16601A OBSOLETE PART DESCRIPTION: The LVC16601A 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. This 18-bit universal bus transceiver com- bines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC16601A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS, 5 VOLT TOLERANT I/O CLKAB B1 OEAB LEAB LEBA CLKENBA 54 1 56 55 2 28 30 29 27 3 CLKBA OEBA A1 CLKENAB CE 1D C1 CLK CE 1D C1 CLK TO 17 OTHER CHANNELS OBSOLETE P ART NOT RECOMMENDED FOR NEW DESIGNS |
类似零件编号 - 74LVC16601APVG |
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类似说明 - 74LVC16601APVG |
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