FXPS7115D4 datasheet(35/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit

Symbol

Description

ENDINIT

The ENDINIT bit is a control bit used to indicate that the user has completed all device and

system level initialization tests. Once the ENDINIT bit is set, writes to all writable register bits

are inhibited except for the DEVLOCK_WR register. Once set, the ENDINIT bit can only be

cleared by a device reset.

When ENDINIT is set, the following occurs:

• An error detection is enabled for all user writable registers. The error detection code is

continuously calculated on the user writable registers and verified against a previously

calculated error detection code.

• Self-test is disabled and inhibited.

• Register writes are inhibited except for the RESET[1:0] bits in the DEVLOCK_WR register.

SUP_ERR_DIS

The supply error disable bit allows the user to disable reporting of the supply errors in the SPI

status fields.

In SPI Mode:

• 0: No Response until the supply monitor timer expires. The Sensor Data Field Error Code

is transmitted for one response after the supply monitor timer expires. All supply errors

are cleared by a read of the DEVSTAT1 register through any communication interface or

on a data transmission that includes the error in the status field if and only if the timer has

reached zero.

• 1: No Responses occur if the timer is non-zero. The error is cleared when the timer reaches

zero and normal transmissions resume.

In I2C Mode (0 or 1):

• No response until the supply monitor timer expires.

• All supply errors are cleared by a read of the DEVSTAT1 register.

1 to 0 RESET[1:0]

To reset the device, three consecutive register write operations must be performed in the order

shown in Table 48, or the device will not reset.[1]

Table 47. DEVLOCK_WR - lock register writes register (address 10h) bit description

[1]

After POR and/or soft reset, see Section 7.5.5 for initialization sequence.

RESET[0]

RESET[1]

Effect

No effect

Device RESET

Table 48. Device reset command sequence

The response to a register write returns the new register value, including the values written to the RESET[1:0]

bits. After the third register write command, the device initiates a reset and therefore does not transmit a

response to this command or an acknowledge in I2C mode. The response to a register read returns '00' for

RESET[1:0] and terminates the reset sequence. The reset control bits are not included in the read/write array

error detection.

7.7.5 WRITE_OTP_EN – write OTP enable register (address 11h)

The write OTP enable register is a user programmed read/write register that allows the user to write the

contents of the user programmed OTP array mirror registers to the OTP registers. This register is included in

the user read/write array error detection.

This register is readable and writable in SPI and I2C modes.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.1 — 7 June 2023

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