ST72325 datasheet(7/193 Pages) STMICROELECTRONICS

7 / 193 page

ST72325

7/193

1 INTRODUCTION

The ST72F325 Flash and ST72325 ROM devices

are members of the ST7 microcontroller family de-

signed for mid-range applications.

They are derivatives of the ST72321 and ST72324

devices, with enhanced characteristics and robust

Clock Security System.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM pro-

gram memory.

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption when the application

is in idle or stand-by state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

The devices feature an on-chip Debug Module

(DM) to support in-circuit debugging (ICD). For a

description of the DM registers, refer to the ST7

ICC Protocol Reference Manual.

Main Differences with ST72321:

– TQFP48 and TQFP32 packages

– Clock Security System

– Internal RC, Readout protection, LVD and PLL

without limitations

– Negative current injection not allowed on I/O port

PB0 (instead of PC6).

– External interrupts have Exit from Active Halt

mode capability.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

OSC1

VPP

CONTROL

PROGRAM

(16K - 60K Bytes1))

VDD

RESET

PORT F

PF7:0

TIMER A

BEEP

RAM

(512 - 2048 Bytes1))

PORT C

10-BIT ADC

VAREF

VSSA

PB7:0

PORT E

PE7:0

(2 bits on C/J/K devices)

SCI

TIMER B

PA7:0

(5 bits on C/J devices)

PORT D

PD7:0

SPI

PC7:0

(8 bits)

VSS

WATCHDOG

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on C/J devices)

(3 bits on K devices)

(6 bits on C/J devices)

(2 bits on K devices)

(6 bits on C/J devices)

(5 bits on K devices)

PORT A

PORT B

PWM ART

I2C

EVD

AVD

(8 bits on AR devices)

TLI

1) ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.

DEBUG MODULE

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