AM79C901AVCT datasheet(53/90 Pages) AMD

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Am79C901A

PR ELI M IN AR Y

HPR24: HomePNA PHY Noise Control 2 Register (Register 24)

Table 32.

HPR24: HomePNA PHY Noise Control 2 Register (Register 24)

HPR25: HomePNA PHY Noise Statistics Register (Register 25)

Table 33.

HPR25: HomePNA PHY Noise Statistics Register (Register 25)

Bits

Name

Description

Read/

Write

Default

Value

15:8

Noise Attack

Sets the attack characteristics of the NOISE

algorithm. High nibble sets number of noise events

needed to raise the NOISE level immediately, while

the low nibble is the number of noise events needed

to raise the level at the end of an 870 ms period.

R/W

7:0

Reserved

Reads will produce undefined results.

RXX

Bits

Name

Description

Read/

Write

Default

Value

(hex)

15:8

Noise Level

This is the digital value of the SLICE_LVL_NOISE

output. It is effectively a measure of the noise level

on the wire and tracks noise by counting the

number of false triggers of the NOISE comparator

in an 800 ms window. When auto-adaptation is

enabled (bit 5 of the PHY_Control Register is

false), this register is updated with the current

NOISE count every 50 ns. When adaptation is

disabled, this register may be written to and is used

to generate both the SLICE_LVL_NOISE and

SLICE_LVL_DATA signals.

R/W

7:0

Peak Level

This is a measurement of the peak level of the last

valid (non-collision) AID received.

R/W

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