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AD5259BCPZ50-R7 数据表(PDF) 12 Page - Analog Devices |
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AD5259BCPZ50-R7 数据表(HTML) 12 Page - Analog Devices |
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12 / 14 page ![]() AD5259 Preliminary Technical Data Rev. PrJ 7/22/04 | Page 12 of 14 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. AD5172 Pin Configuration Table 5. AD5259 Pin Function Descriptions Pin Mnemonic Description 1 W W Terminal. GND ≤ VW ≤ VDD. 2 ADO Programmable Tri-State Address Bit 0 for Multiple Package Decoding. 3 AD1 Programmable Tri-State Address Bit 1 for Multiple Package Decoding. 4 SDA Serial Data Input/Output. 5 SCL Serial Clock Input. Positive edge triggered. 6 VLOGIC Logic power supply. 7 GND Digital Ground. 8 VDD Positive Power Supply. 9 B B Terminal. GND ≤ VB ≤ VDD. 10 A A Terminal. GND ≤ VA ≤ VDD. 1 2 3 4 5 10 9 8 7 6 W AD0 AD1 SDA SCL AD5259 TOP VIEW (Not to Scale) A B VDD GND VLOGIC |
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