AD5259BRMZ100-R7 datasheet(4/14 Pages) AD

部件名	AD5259BRMZ100-R7

功能描述	Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer

PDF	14 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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4 / 14 page

AD5259

Preliminary Technical Data

Rev. PrJ 7/22/04 | Page 4 of 14

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted.)

Table 2.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts)

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time between STOP and START

1.3

µs

tHD;STA Hold Time (Repeated START)

After this period, the first clock pulse is

generated.

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time for Repeated START Condition

0.6

µs

tHD;DAT Data Hold Time

0.9

µs

tSU;DAT Data Setup Time

100

tF Fall Time of Both SDA and SCL Signals

300

tR Rise Time of Both SDA and SCL Signals

300

tSU;STO Setup Time for STOP Condition

t10

0.6

µs

SCL

SDA

t10

Figure 4. I2C Interface Timing Diagram

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