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ICS1893AFILFT 数据表(PDF) 4 Page - Renesas Technology Corp

部件名 ICS1893AFILFT
功能描述  3.3-V 10Base-T/100Base-TX Integrated PHYceiver
PDF  137 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

ICS1893AFILFT 数据表(HTML) 4 Page - Renesas Technology Corp

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ICS1893AF, Rev D 10/26/04
October, 2004
4
Table of Contents
ICS1893AF Data Sheet - Release
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
Table of Contents
Section
Title
Page
Chapter 8
Management Register Set ............................................................................................... 55
8.1
Introduction to Management Register Set ............................................................. 56
8.1.1
Management Register Set Outline ......................................................................... 56
8.1.2
Management Register Bit Access .......................................................................... 57
8.1.3
Management Register Bit Default Values .............................................................. 57
8.1.4
Management Register Bit Special Functions ......................................................... 58
8.2
Register 0: Control Register ................................................................................... 59
8.2.1
Reset (bit 0.15) ......................................................................................................59
8.2.2
Loopback Enable (bit 0.14) .................................................................................... 60
8.2.3
Data Rate Select (bit 0.13) ..................................................................................... 60
8.2.4
Auto-Negotiation Enable (bit 0.12) ......................................................................... 60
8.2.5
Low Power Mode (bit 0.11) .................................................................................... 61
8.2.6
Isolate (bit 0.10) ..................................................................................................... 61
8.2.7
Restart Auto-Negotiation (bit 0.9) .......................................................................... 61
8.2.8
Duplex Mode (bit 0.8) ............................................................................................. 62
8.2.9
Collision Test (bit 0.7) ............................................................................................ 62
8.2.10
IEEE Reserved Bits (bits 0.6:0) ............................................................................. 62
8.3
Register 1: Status Register .................................................................................... 63
8.3.1
100Base-T4 (bit 1.15) ............................................................................................ 63
8.3.2
100Base-TX Full Duplex (bit 1.14) ......................................................................... 64
8.3.3
100Base-TX Half Duplex (bit 1.13) ........................................................................ 64
8.3.4
10Base-T Full Duplex (bit 1.12) ............................................................................. 64
8.3.5
10Base-T Half Duplex (bit 1.11) ............................................................................. 64
8.3.6
IEEE Reserved Bits (bits 1.10:7) ........................................................................... 65
8.3.7
MF Preamble Suppression (bit 1.6) ....................................................................... 65
8.3.8
Auto-Negotiation Complete (bit 1.5) ....................................................................... 65
8.3.9
Remote Fault (bit 1.4) ............................................................................................ 66
8.3.10
Auto-Negotiation Ability (bit 1.3) ............................................................................66
8.3.11
Link Status (bit 1.2) ................................................................................................ 67
8.3.12
Jabber Detect (bit 1.1) ........................................................................................... 67
8.3.13
Extended Capability (bit 1.0) ..................................................................................67
8.4
Register 2: PHY Identifier Register ........................................................................ 68



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