ICS8430S07AKI REVISION A SEPTEMBER 3, 2009

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©2009 Integrated Device Technology, Inc.

ICS8430S07I Data Sheet

CLOCK GENERATOR FOR CAVIUM PROCESSORS

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 9.

Figure 9. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of

VDD – 2V.

•

For logic high, VOUT = VOH_MAX = VDD_MAX – 0.9V

(VDD_MAX – VOH_MAX) = 0.9V

•

For logic low, VOUT = VOL_MAX = VDD_MAX – 1.7V

(VDD_MAX – VOL_MAX) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/RL] * (VDD_MAX – VOH_MAX) =

[(2V – 0.9V)/50

Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/RL] * (VDD_MAX – VOL_MAX) =

[(2V – 1.7V)/50

Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

V

OUT

V

CC

V

CC - 2V

Q1

RL

50

Ω