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©2016 Integrated Device Technology, Inc

Revision B June 28, 2016

831752 Data Sheet

Table 1. Pin Descriptions

NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Table

Table 3. Direction Control Function Table

NOTE: X = 0 or 1

Number

Name

Type

Description

1

DIR_SEL

Input

Pulldown

Direction control for the FCLK I/O. Works in conjunction with nOEFCLK.

See Table 3 for function. LVCMOS/LVTTL interface levels.

2

nOEFCLK

Input

Pullup

Output enable for the FCLK I/O output. Works in conjunction with

DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels.

3, 10, 14

VDD

Power

Core and output power supply pin.

4, 5

FCLK, nFCLK

I/O

Differential I/O. Signal direction is controlled by DIR_SEL. Accepts

differential signals when operating as an input. Differential HCSL

signals when operating as an output. Internal source termination can be

disabled. See Table 3 for function.

6, 11, 15

GND

Power

Power supply ground.

7

CLK

Input

Pulldown

Non-inverting input.

8

nCLK

Input

Pulldown/Pullup

Inverting differential clock input.

9

nc

Unused

No connect.

12, 13

nQ, Q

Output

Differential output pair. HCSL interface levels.

16

IREF

Input

An external fixed precision resistor (475

) from this pin to ground

provides a reference current used for the differential current-mode Q

and FCLK outputs.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4pF

RPULLDOWN Input Pulldown Resistor

51

k



RPULLUP

Input Pullup Resistor

51

k



Input

Input

Operation

FCLK Function

DIR_SEL

nOEFCLK

00

Local clock mode 0. The input signal at CLK is routed to

both outputs Q and FCLK.

Differential HCSL output with internal 50

 source

termination

0 (default)

1 (default)

Local clock mode 1. The input signal at CLK is routed to

the output Q.

Output is disabled (high impedance). Internal 50



termination is disabled.

1X

Common reference clock mode. FCLK is the clock input.

Q is the clock output.

Differential clock input. Internal 50

 source

termination is disabled as well as output driver and

22.33

 resistors.