ADIS16203SLASHPCBZ datasheet(5/28 Pages) AD

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ADIS16203

Rev. 0 | Page 5 of 28

TIMING SPECIFICATIONS

TA = +25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.

Table 2.

Parameter

Description

Min1

Typ

Max

Unit

fSCLK

Fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz)

0.01

2.5

MHz

Normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz)

0.01

1.0

MHz

tDATARATE

Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz)

μs

Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz)

100

μs

tCS

Chip select to clock edge

48.8

tDAV

Data output valid after SCLK falling edge2

100

tDSU

Data input setup time before SCLK rising edge

24.4

tDHD

Data input hold time after SCLK rising edge

48.8

tDF

Data output fall time

12.5

tDR

Data output rise time

12.5

tSFS

CS high after SCLK edge3

1 Guaranteed by design, not production tested.

2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are

governed by this specification.

3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.

TIMING DIAGRAMS

SCLK

tDATARATE

tSTALL = tDATARATE – 16/fSCLK

tSTALL

Figure 2. SPI Chip Select Timing

SCLK

DOUT

DIN

W/R

MSB

DB14

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

tCS

tSFS

tDAV

tDHD

tDSU

Figure 3. SPI Timing, Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1

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