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July 2004

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5V TOLERANT INPUTS

s

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POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

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SYMMETRICAL OUTPUT IMPEDANCE:

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PCI BUS LEVELS GUARANTEED AT 24 mA

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

Retention)

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

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LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

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ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LVC573A is a low voltage CMOS OCTAL

D-TYPE LATCH fabricated with sub-micron silicon

operations

and

low

power

and

low

noise

applications.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input precisely or

inversely. When the LE is taken low, the Q outputs

will be latched precisely or inversely at the logic

level of D input data. While the (OE) input is low,

the 8 outputs will be in a normal logic state (high or

low logic level) and while high level the outputs will

be in a high impedance state.

This device is designed to interface directly High

Speed CMOS systems with TTL and NMOS

components. It has more speed performance at

3.3V than 5V AC/ACT family, combined with a

lower power consumption.

All inputs are equipped with protection circuits

against static discharge, giving them 2KV ESD

immunity and transient excess voltage.

74LVC573A

OCTAL D-TYPE LATCH

HIGH PERFORMANCE

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LVC573AMTR

TSSOP

74LVC573ATTR

TSSOP

SOP

Rev. 3