AM29BL162C datasheet(13/50 Pages) SPANSION

13 / 50 page

July 8, 2005

Am29BL162C

DA T A

SH EET

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3 V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL

but not within VSS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the inter-

nal reset operation is complete, which requires a time of

tREADY (during Embedded Algorithms). The system can

thus monitor RY/BY# to determine whether the reset op-

eration is complete. If RESET# is asserted when a pro-

gram or erase operation is not executing (RY/BY# pin is

“1”), the reset operation is completed within a time of

tREADY (not during Embedded Algorithms). The system

can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 17 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2.

Sector Address Table

Sector

Sector Size

A19

A18

A17

A16

A15

A14

A13

A12

Address Range

SA0

8 Kwords

0000000

00000h–01FFFh

SA1

4 Kwords

00000010

02000h–02FFFh

SA2

4 Kwords

00000011

03000h–03FFFh

SA3

112 Kwords

00100–11111

04000h–1FFFFh

SA4

128 Kwords

XXXXX

20000h–3FFFFh

SA5

128 Kwords

XXXXX

40000h–5FFFFh

SA6

128 Kwords

XXXXX

60000h–7FFFFh

SA7

128 Kwords

XXXXX

80000h–9FFFFh

SA8

128 Kwords

XXXXX

A0000h–BFFFFh

SA9

128 Kwords

XXXXX

C0000h–DFFFFh

SA10

128 Kwords

XXXXX

E0000h–FFFFFh

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