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MPC850 数据表(PDF) 35 Page - Freescale Semiconductor, Inc |
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MPC850 数据表(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 35 Bus Signal Timing Table 9 shows the PCMCIA port timing for the MPC850. Figure 27 provides the PCMCIA output port timing for the MPC850. Figure 27. PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC850. Figure 28. PCMCIA Input Port Timing Table 9. PCMCIA Port Timing Num Characteristic 50 MHz 66 MHz 80 MHz Unit Min Max Min Max Min Max P57 CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 ns P58 HRESET negated to OPx drive 1 1 OP2 and OP3 only. 18.00 — 26.00 — 22.00 — ns P59 IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — ns P60 CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — ns CLKOUT HRESET Output Signals OP2, OP3 P57 P58 CLKOUT Input Signals P59 P60 |
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