87949AYI-01

www.idt.com

REV. A AUGUST 10, 2010

ICS87949I-01

LOW SKEW

÷1, ÷2

LVCMOS / LVTTL CLOCK GENERATOR

1

GENERAL DESCRIPTION

The ICS87949I-01 is a low skew, ÷1, ÷2 Clock Generator.

The ICS87949I-01 has selectable single ended clock or

LVPECL clock inputs. The single ended clock input accepts

LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can

accept LVPECL, CML, or SSTL input levels. The low

impedance LVCMOS/LVTTL outputs are designed to drive

50

Ω series or parallel terminated transmission lines. The

effective fanout can be increased from 15 to 30 by utilizing

the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output

frequency of each bank. The outputs can be utilized in the

÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master

reset input, MR/nOE, resets the internal frequency dividers

and also controls the active and high impedance states of

all outputs.

The ICS87949I-01 is characterized at 3.3V core/3.3V output

and 3.3V core/2.5V output. Guaranteed bank, output and

part-to-part skew characteristics make the ICS87949I-01 ideal

for those clock distribution applications demanding well

defined performance and repeatability.

FEATURES

• 15 single ended LVCMOS/LVTTL outputs,

7

Ω typical output impedance

• Selectable LVCMOS/LVTTL or LVPECL clock inputs

• CLK0 and CLK1 can accept the following input levels:

LVCMOS and LVTTL

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• Maximum input frequency: 250MHz

• Output skew: 250ps (maximum)

• Part-to-part skew: 1ns (maximum)

• Full 3.3V or mixed 3.3V core/2.5V output supply

• -40°C to 85°C ambient operating temperature

• Functionally compatible to the MPC949 in a smaller footprint

requiring less board space

BLOCK DIAGRAM

PIN ASSIGNMENT

48-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

MR/nOE

CLK_SEL

VDD

CLK0

CLK1

PCLK

nPCLK

PCLK_SEL

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

1

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

36

35

34

33

32

31

30

29

28

27

26

25

48 47 46 45 44 43 42 41 40 39 38 37

nc

GND

QC0

VDDC

QC1

GND

QC2

VDDC

QC3

GND

GND

QD5

ICS87949I-01

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

MR/nOE

QA0, QA1

QB0:QB2

QC0:QC3

QD0:QD5

CLK_SEL

CLK0

CLK1

PCLK

nPCLK

PCLK_SEL

0

1

÷1

÷2

0

1

0

1

0

1

0

1

R

0

1