ICS93701

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1,7,8,18,24,25,

GND

PWR

Ground

31,41,42,48

26,30,40,43,47, CLKC(9:0)

OUT

"Complementary" clocks of differential pair outputs.

23,19,9,6,2

27,29,39,44,46,

CLKT (9:0)

OUT

"True" Clock of differential pair outputs.

22,20,10,5,3

4,11,21,28,

VDD

PWR

Power supply 2.5V

34,38,45,

12

SCLK

IN

Clock input of l2C input,5V tolerant input

13

CLK_INT

IN

"True" reference clock input

14

CLK_INC

IN

"Complementary" reference clock input

15

VDDl2C

PWR

3.3V power for 12

c

16

AVDD

PWR

Analog power supply,2.5V

17

AGND

PWR

Analog ground.

"Complementary" Feedback output,dedicated for external feedback. It

32

FB_OUTC

OUT

switches at the same frequency as the CLK. This output must be wired

to FB_INC.

"True" " Feedback output,dedicated for external feedback. It switches

33

FB_OUTT

OUT

at the same frequency as the CLK. This output must be wired to

FB_INT.

35

FB_INT

IN

"True" Feedback input,provides feedback signal to the internal PLL for

synchronization with CLK_INT to eliminate phase error.

36

FB_INC

IN

"Complementary" Feedback input,provides signal to the internal PLL

for synchronization with CLK_INC to eliminate phase error.

37

SDATA

IN Data input for 12C serial input,5V tolerant input

0417B---10/29/02

2