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ICS93716 数据表(PDF) 1 Page - Renesas Technology Corp

部件名 ICS93716
功能描述  Low Cost DDR Phase Lock Loop Clock Driver
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

ICS93716 数据表(HTML) 1 Page - Renesas Technology Corp

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ICS93716
0420H—09/10/08
Block Diagram
Low Cost DDR Phase Lock Loop Clock Driver
Pin Configuration
28-Pin SSOP and TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
•
Low skew, low jitter PLL clock driver
•I
2C for functional and output control
•
Feedback pins for input to output synchronization
•
Spread Spectrum tolerant inputs
•
Bypass mode on B revision only
Switching Characteristics:
•
PEAK - PEAK jitter (66MHz): <75ps
•
CYCLE - CYCLE jitter (>100MHz):<65ps
•
OUTPUT - OUTPUT skew: <100ps
•
Output Rise and Fall Time: 550ps - 950ps
Functionality
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
L
P
D
D
V
AT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
U
O
_
B
F
V
5
.
2
)
m
o
n
(
LH
L
H
L
H
n
o
V
5
.
2
)
m
o
n
(
HL
H
L
H
L
n
o
V
5
.
2
)
m
o
n
(
z
H
M
0
2
<Z
Z
Z
Z
f
f
o
D
N
GL
H
L
H
L
H
f
f
o
/
d
e
s
s
a
p
y
B
D
N
GH
L
H
L
H
L
f
f
o
/
d
e
s
s
a
p
y
B
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
PLL
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FB_OUTT
FB_OUTC
CLKT3
CLKC3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15


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