ICS94201 datasheet(1/20 Pages) RENESAS

部件名	ICS94201

功能描述	Programmable System Frequency Generator for PII/III™

PDF	20 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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1 / 20 page

Integrated

Circuit

Systems, Inc.

ICS94201

0428B- 11/28/05

Pin Configuration

Recommended Application:

810/810E and Solano (815) type chipset

Output Features:

•

2 - CPUs @ 2.5V

•

13 - SDRAM @ 3.3V

•

3 - 3V66 @ 3.3V

•

8 - PCI @3.3V

•

1 - 24/48MHz@ 3.3V

•

1 - 48MHz @ 3.3V fixed

•

1 - REF @3.3V, 14.318MHz

Features:

•

Programmable ouput frequency.

•

Programmable ouput rise/fall time for PCI

and SDRAM clocks.

•

Programmable 3V66 to PCI skew.

•

Spread spectrum for EMI control

with programmable spread percentage.

•

Watchdog timer technology to reset system

if over-clocking causes malfunction.

•

Support power management through PD#.

•

Uses external 14.318MHz crystal.

•

FS pins for frequency select

Key Specifications:

•

CPU Output Jitter: <250ps

•

IOAPIC Output Jitter: <500ps

•

48MHz, 3V66, PCI Output Jitter: <500ps

•

CPU Output Skew: <175ps

•

PCI Output Skew: <500ps

•

3V66 Output Skew <175ps

•

For group skew timing, please refer to the

Group Timing Relationship Table.

Programmable System Frequency Generator for PII/III™

56-Pin 300 mil SSOP

1. These pins will have 1.5 to 2X drive strength.

* 120K ohm pull-up to VDD on indicated inputs.

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK [1:0]

2

12

8

3

SDRAM [11:0]

IOAPIC

PCICLK [7:0]

SDRAM_F

3V66 [2:0]

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

FS[4:0]

PD#

SEL24_48#

SDATA

SCLK

Control

Logic

Config.

Reg.

/ 2

REF0

Block Diagram

VDDREF

X1

X2

GNDREF

GND3V66

3V66-1

3V66-2

VDD3V66

VDDPCI

*(FS0)PCICLK0

*(FS1)PCICLK1

*(SEL24_48#)PCICLK2

GNDPCI

PCICLK3

PCICLK4

PCICLK5

VDDPCI

PCICLK6

PCICLK7

GNDPCI

PD#

SCLK

SDATA

VDDSDR

SDRAM11

SDRAM10

GNDSDR

3V66-0

1

REF0(FS4)*

VDDLAPIC

IOAPIC

VDDLCPU

CPUCLK0

CPUCLK1

GNDLCPU

GNDSDR

SDRAM0

SDRAM1

SDRAM2

VDDSDR

SDRAM3

SDRAM4

SDRAM5

GNDSDR

SDRAM6

SDRAM7

SDRAM_F

VDDSDR

GND48

24_48MHz(FS2)*

48MHz(FS3)*

VDD48

VDDSDR

SDRAM8

SDRAM9

GNDSDR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

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