6

ICS950401

0499C—11/01/04

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B6

3

,

7

31

)

e

t

o

N

(

1

_

C

/

T

K

L

C

U

P

C

6

t

i

B0

4

,

1

41

0

_

C

/

T

K

L

C

U

P

C

5

t

i

B5

41

2

F

E

R

4

t

i

B8

41

1

F

E

R

3

t

i

B1

1

0

F

E

R

2

t

i

B8

21

z

H

M

8

4

_

4

2

1

t

i

B1

31

z

H

M

8

4

0

t

i

B1

11

2

_

6

6

/

3

3

K

L

C

I

C

P

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

Byte 4: Read-Back Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

D

I

R

O

D

N

E

V

6

t

i

B-

0

5

t

i

B-

1

4

t

i

B-

0

D

I

N

O

I

S

I

V

E

R

3

t

i

B-

0

2

t

i

B-

0

1

t

i

B-

0

0

t

i

B-

0

Byte 5: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

)

e

t

o

N

(

7

e

t

y

B

6

t

i

B-

0

)

e

t

o

N

(

6

e

t

y

B

5

t

i

B-

0

)

e

t

o

N

(

5

e

t

y

B

4

t

i

B-

0

)

e

t

o

N

(

4

e

t

y

B

3

t

i

B-

0

)

e

t

o

N

(

3

e

t

y

B

2

t

i

B-

1

)

e

t

o

N

(

2

e

t

y

B

1

t

i

B-

1

)

e

t

o

N

(

1

e

t

y

B

0

t

i

B-

1

)

e

t

o

N

(

0

e

t

y

B

Byte 6: Byte Count Register

(1= enable, 0 = disable)

Note: Writing to this register will configure byte count

and how many bytes will be read back. Default

state is 07H = 7 bytes.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

)

d

e

v

r

e

s

e

R

(

6

t

i

B-

0

)

d

e

v

r

e

s

e

R

(

5

t

i

B2

20

)

e

t

o

N

(

5

K

L

C

I

C

P

4

t

i

B1

20

)

e

t

o

N

(

4

K

L

C

I

C

P

3

t

i

B8

10

)

e

t

o

N

(

3

K

L

C

I

C

P

2

t

i

B7

10

)

e

t

o

N

(

2

K

L

C

I

C

P

1

t

i

B4

10

)

e

t

o

N

(

1

K

L

C

I

C

P

0

t

i

B3

10

)

e

t

o

N

(

0

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B7

1

1

_

6

6

/

3

3

K

L

C

I

C

P

6

t

i

B8

1

0

_

6

6

/

3

3

K

L

C

I

C

P

5

t

i

B2

21

5

K

L

C

I

C

P

4

t

i

B1

21

4

K

L

C

I

C

P

3

t

i

B8

11

3

K

L

C

I

C

P

2

t

i

B7

11

2

K

L

C

I

C

P

1

t

i

B4

11

1

K

L

C

I

C

P

0

t

i

B3

11

0

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B

3

2

1)

e

t

o

N

(

F

_

K

L

C

I

C

P

6

t

i

B

4

4

1D

A

E

R

P

S

5

t

i

B

8

2

1L

E

S

8

4

_

4

2

4

t

i

B

6

1#

L

E

S

6

6

/

3

3

I

C

P

3

t

i

B

5

4

1e

t

a

t

s

n

i

p

d

e

h

c

t

a

l

p

u

-

r

e

w

o

p

2

S

F

2

t

i

B

8

4

1e

t

a

t

s

n

i

p

d

e

h

c

t

a

l

p

u

-

r

e

w

o

p

1

S

F

1

t

i

B

1

1e

t

a

t

s

n

i

p

d

e

h

c

t

a

l

p

u

-

r

e

w

o

p

0

S

F

0

t

i

B

-

0)

d

e

v

r

e

s

e

R

(

Note: This bit can be optional to disable the CPUCLKT/

C1 clock pair; CPUCLKT=L, CPUCLKC=H.

Note: Can be optionally used as PCI33_F enable

control.

Note: The above individual free running enable/disable

controls are intended to allow individual clock

outputs to be made free running. A clock output

that has it's free running bit enabled will not be

turned off with the assertion of either PCI_STOP#.