LP5866TRKPR datasheet(64/71 Pages) TI

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9.2.3 Detailed Design Procedure

LP5861T requires an external capacitor CVCAP, whose value is 1 μF connected from VCAP to GND for proper

operation of internal LDO. The external capacitor must be placed as close to the device as possible.

TI recommends 1-μF capacitors to be placed between VCC / VLED with GND, and 1-nF capacitor placed

between VIO with GND. Place the capacitors as close to the device as possible.

Pullup resistors Rpull-up are requirement for SCL and SDA when using I2C as communication method. In typical

applications, TI recommends 1.8-kΩ to 4.7-kΩ resistors.

To decrease thermal dissipation from device to ambient, resistors RCS an optionally be placed in serial with the

LED. Voltage drop on these resistors must leave enough margins for VSAT to ensure the device work normally.

9.2.3.1 Program Procedure

When selecting data refresh Mode 1, outputs are refreshed instantly after data is received.

When selecting data refresh Mode 2 and 3, VSYNC signal is required for synchronized display. Programming

flow is showed as Figure 9-2. To display full pixel of last frame, VSYNC pulse must be sent to the device after

the end of last PWM. Time between two pulses tSYNC must be larger than the whole PWM time of all Dots tframe.

Common selection like 60 Hz, 90 Hz, 120 Hz or even higher refresh frequency can be supported. High pulse

width longer than tSYNC_H is required at the beginning of each VSYNC frame, and data must not be write to PWM

registers during high pulse width.

Power up VCC /

VIO / VLED

Config initialization

registers

Write frame data

Send VSYNC pulse

Write frame data of

next frame

Update frame?

Figure 9-2. Program Procedure

LP5861T

SNVSCE4 – MAY 2023

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LP5866TRKPR 数据表(PDF) 64 Page - Texas Instruments