GL823K Datasheet

© 2014 Genesys Logic, Inc. - All rights reserved.

Page 10

GLI Confidential

CHAPTER 4

BLOCK DIAGRAM

EHCI

EP0/EP3 FIFO

BULK FIFO

EPFIFO

8051

CORE

Control

Register

RAM

ROM

MHE

SD 4bit I/F

SIE

OCCS

USB PHY

Regulator

5 to 3.3V

3.3 to 1.8V

MSPRO 4bit

I/F

Table 4.1 – Functional Block Diagram

4.1 OCCS USB PHY

The USB 2.0 Transceiver Macrocell is the analog circuitry that handles the low level USB protocol and signaling,

and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. On

chip clock source and no need of 12MHz Crystal Clock input.

4.2 SIE

The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing

and state machine logic to handle USB packets and transactions.

4.3 EPFIFO

Endpoint FIFO includes Control FIFO (FIFO0) and Bulk In/Out FIFO

 EP0 FIFO

FIFO of control endpoint 0. It is 64-byte FIFO and used for endpoint 0 data transfer.

 Interrupt FIFO

64-byte depth FIFO of endpoint 3 for status interrupt

 Bulk FIFO

It can be in the TX mode or RX mode:

1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.

2. It can be directly accessed by micro-controller

4.4 MCU

8051 micro-controller inside.

 8051 Core

Compliant with Intel 8051 high speed micro-controller

 ROM

FW code on ROM

 SRAM

Internal RAM area for MCU access