ICS8714008I datasheet(21/35 Pages) RENESAS

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ICS8714008I DATA SHEET

FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET

ICS8714008DKI REVISION A NOVEMBER 25, 2013

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other

differential signals. Both signals must meet the VPP and VCMR input

requirements. Figures 4A to 4F show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the

vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 4A, the input termination

applies for IDT open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 4A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 4C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 4E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 4B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

Figure 4F. CLK/nCLK Input Driven by a

3.3V MLVDS Driver

1.8V

Zo = 50

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

3.3V

CLK

nCLK

3.3V

LVPECL

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

Differential

Input

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

3.3V

100

MLVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

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