6.42

IDT709359/49L

High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

2

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 9796 9594 93 9291 9089 8887 8685 8483 82 8180 7978 7776

100-Pin TQFP

Top View(6)

A9L

A10L

A11L

A12L(1)

NC

NC

NC

LBL

UBL

CE0L

CE1L

CNTRSTL

R/

WL

OEL

VCC

FT/PIPEL

I/O16L

I/O17L

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

5633 drw 02

A8R

A9R

A10R

A11R

A12R(1)

NC

NC

NC

LBR

UBR

CE0R

CNTRSTR

R/

WR

GND

OER

FT/PIPER

I/O14R

I/O13R

I/O12R

I/O11R

CE1R

I/O17R

GND

I/O16R

I/O15R

709359/49PF

PN100(5)

Pin Configurations(1,2,3,4)

NOTES:

1. A12 is a NC for IDT709349.

2. All VCC pins must be connected to power supply.

3. All GND pins must be connected to ground.

4. Package body is approximately 14mm x 14mm x 1.4mm

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

Description

TheIDT709359/49isahigh-speed8/4Kx18bitsynchronousDual-

Port RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold

times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times.

Withaninputdataregister,theIDT709359/49hasbeenoptimizedfor

applications having unidirectional or bidirectional data flow in bursts.

An automatic power down feature, controlled by CE0and CE1, permits

the on-chip circuitry of each port to enter a very low standby power

mode. Fabricated using CMOS high-performance technology, these

devices typically operate on only 925mW of power.