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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

JTAG Configuration Register Access

As previously mentioned, the JTAG port may be used to read and write to the CPS-10Q’s configuration registers. The same JTAG instruction (4b1010)

is used for both writes and reads.

Writes during Configuration Register Access

A write is performed by shifting the CRA OPcode into the Instruction Register (IR), then shifting in first a read / write select bit, then both the 22-bit

target address and 32-bit data into the Data Register (DR). When bit 0 of the data stream is 0, data shifted in after the address will be written to the

address specified in jtag_config_addr. The TDO pin will transmit all 0s. See the figure below for the associated timing diagram.

Figure 25 Implementation of write during configuration register access

Bits

Field Name Size

Description

0

jtag_config_wr_n

1

1 – read configuration register

0 – write configuration register

Bits

Field Name Size

Description

[22:1]

jtag_config_addr

22

Starting address of the memory mapped configuration register. 22 address bits map to a unique double-word aligned on

a 32-bit boundary. This provides accessibility to and is consistent with the sRIO memory mapping.

[54:23]

jtag_config_data

32

Reads: Data shifted out (one 32-bit word per read) is read from the configuration register at address jtag_config_addr.

Writes: Data shifted in (one 32-bit word per write) is written to the configuration register at address jtag_config_addr.

Table 33 Data Stream for JTAG Configuration Register Access Mode

Shift_dr

Capture _dr

Shift_dr

Pause_dr

Exit1_dr

Exit2_dr

Update_dr

Exit1_dr

Exit2_dr

Pause_dr

Select_dr_scan

TAP controller

state

TDO

ZZ

Z

Internal

address

Address

Internal

data

Data

Address

Data

TDI