5

HT6256

READ CYCLE AC TIMING CHARACTERISTICS (1)

(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels

shown in the Tester AC Timing Characteristics table, capacitive output loading C

TSHQZ and TGHQZ. For C

(2) Typical operating conditions: VDD=5.0 V, TA=25

°C.

(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 225

°C.

(4) External control of Chip Enable (CE) is available only in other package options.

Symbol

Parameter

Typical (2)

Worst Case (3)

Units

Min

Max

TAVAVR

Address Read Cycle Time

50

ns

TAVQV

Address Access Time

50

ns

TAXQX

Address Change to Output Invalid Time

3

ns

TSLQV

Chip Select Access Time

50

ns

TSLQX

Chip Select Output Enable Time

5

ns

TSHQZ

Chip Select Output Disable Time

20

ns

TGLQV

Output Enable Access Time

15

ns

TGLQX

Output Enable Output Enable Time

0

ns

TGHQZ

Output Enable Output Disable Time

15

ns

TEHQV

Chip Enable Output Access Time (4)

17

25

ns

TEHQX

Chip Enable Output enable Time (4)

10

5

ns

TELQZ

Chip Enable Output Disable Time (4)

4

10

ns

HIGH

IMPEDANCE

NCS

NOE

DATA VALID

CE

ADDRESS

(NWE = high)

DATA OUT