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WMS7204 数据表(PDF) 19 Page - Winbond |
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WMS7204 数据表(HTML) 19 Page - Winbond |
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19 / 32 page ![]() WMS7204 Publication Release Date: January 2003 - 19 - Revision 1.0 TABLE 10 – TIMING PARAMETERS Note: The interface timing characteristics apply to all parts but are guaranteed by design and not subject to production test. PARAMETER SYMBOL MIN. MAX. UNIT SPI Clock Cycle Time tCYC 100 ns SPI Clock HIGH Time tWH 50 ns SPI Clock LOW Time tWL 50 ns Lead Time tLEAD 100 ns Lag Time tLAG 100 ns SDI Setup Time tDSU 20 ns SDI Hold Time tDH 20 ns CS to SDO – SPI Line Acquire tLAC 5 ns CS to SDO – SPI Line Release tLRL 5 ns CLK to SDO Propagation Delay tPD 1 ns R/B Rise to CS Fall tRSU 500 ns Store to NVMEM Save Time tSV 2 ms CS Deselect Time tCS 600 ns Startup Time tST 0.1 ms WP Setup Time tWPSU 10 ns WP Hold Time tWPH 10 ns |
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