Preliminary Technical Data

ADCMP608/ADCMP609

Rev. PrA | Page 11 of 16

The hysteresis control pin appears as a 1.25 V bias voltage seen

through a series resistance of 7k ± 20% throughout the

hysterisis control range. The advantages of applying hysteresis

in this manner are improved accuracy, improved stability,

reduced component count, and maximum versatility. An

external bypass capacitor is not recommended on the HYS pin

because it would likely degrade the jitter performance of the

device and impair the latch function. As described in

CROSSOVER BIAS POINT

Rail-to-rail inputs of this type, in both op amps and compara-

tors have a dual front-end design. Certain devices are active

predetermined point in the common-mode range, a crossover

current reverses and there are changes in measured offset

voltages and currents.

Using/Disabling the Latch Feature, hysteresis control need not

compromise the latch function.

5 V. This means that the comparator input characteristics will

more closely resemble the inputs of non rail-to rail ground

sensing comparators such as the AD8611.

MINIMUM INPUT SLEW RATE REQUIREMENT

(Remove if device is stable.)

As with most high speed comparators, without hysteresis a

minimum slew rate must be met to ensure that the device does

not oscillate as the input signal crosses the threshold. This

oscillation is due to the high gain bandwidth of the comparator

in combination with feedback parasitics inherent in the package

and PC board. A minimum slew rate of TBD. V/μs ensures

clean output transitions from the ADCMP608/ADCMP609

comparators without hysteresis. In many applications,

chattering is not harmful.