ADL5519ACPZ-R2 datasheet(13/27 Pages) AD

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Preliminary Technical Data

ADL5519

Rev. PrB | Page 13 of 27

THEORY OF OPERATION

The ADL5519 is a dual-channel 6-stage demodulating

logarithmic amplifier, specifically designed for use in RF

measurement and power control applications at frequencies

up to 10 GHz. Sharing much of its design with the AD8317

logarithmic detector/controller, the ADL5519 maintains tight

intercept variability vs. temperature over a 50 dB range. Each

measurement channel offers equivalent performance to the

AD8317. The complete circuit block diagram is shown in

Figure 9.

CHANNEL A

Log Detector

CHANNEL B

Log Detector

INHB

INLB

COMR

PWDN

INLA

INHA

OUTB

FBKB

OUTN

OUTP

FBKA

OUTA

BIAS

TEMP

OUTB

OUTA

COMR

Figure 9. Block Diagram

Each measurement channel is a fully differential design

and uses a proprietary, high speed SiGe process, extending

high frequency performance. Figure 10 shows the basic

diagram of the ADL5519’s channel A signal path, the

functionality is identical for channel B.

DET

INHA

INLA

OUTA

VSTA

CLPA

Figure 10. Single Channel Block Diagram

The maximum input with ±1 dB log-conformance error is

typically 0 dBm (re: 50 Ω). The noise spectral density referred

to the input is 1.15 nV/√Hz, which is equivalent to a voltage of

118 μV rms in a 10.5 GHz bandwidth or a noise power of −66

dBm (re: 50 Ω). This noise spectral density sets the lower limit

of the dynamic range. However, the low end accuracy of the

ADL5519 is enhanced by specially shaping the demodulating

transfer characteristic to partially compensate for errors due to

internal noise. The common pin, COMR, provides a quality low

impedance connection to the printed circuit board (PCB) ground.

The package paddle, which is internally connected to the

COMR pin, should also be grounded to the PCB to reduce

thermal impedance from the die to the PCB.

The logarithmic function is approximated in a piecewise

fashion by six cascaded gain stages. (For a more comprehensive

explanation of the logarithm approximation, please refer to the

AD8307 data sheet, available at www.analog.com.) The cells

have a nominal voltage gain of 9 dB each and a 3 dB bandwidth

of 10.5 GHz. Using precision biasing, the gain is stabilized over

temperature and supply variations. The overall dc gain is high,

due to the cascaded nature of the gain stages. An offset

compensation loop is included to correct for offsets within the

cascaded cells. At the output of each of the gain stages, a square-

law detector cell is used to rectify the signal.

The RF signal voltages are converted to a fluctuating differential

current having an average value that increases with signal level.

Along with the six gain stages and detector cells, an additional

detector is included at the input of each measurement channel,,

providing a 50 dB dynamic range in total. After the detector

currents are summed and filtered, the following function is

formed at the summing node:

ID × log10(VIN/VINTERCEPT)

where:

ID is the internally set detector current.

VIN is the input signal voltage.

VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,

the output voltage would be 0 V, if it were capable of going to 0 V).

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