CS5422

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13

Both logic level and standard FETs can be used.

Voltage applied to the FET gates depends on the

application circuit used. Both upper and lower gate driver

outputs are specified to drive to within 1.5 V of ground when

in the low state and to within 2.0 V of their respective bias

supplies when in the high state. In practice, the FET gates

will be driven rail−to−rail due to overshoot caused by the

capacitive load they present to the controller IC.

Selection of the Switching (Upper) FET

The designer must ensure that the total power dissipation

in the FET switch does not cause the power component’s

junction temperature to exceed 150°C.

The maximum RMS current through the switch can be

determined by the following formula:

IRMS(H) +

IL(PEAK)2 ) (IL(PEAK)

IL(VALLEY))

) IL(VALLEY)2

D

3

where:

D = duty cycle.

Once the RMS current through the switch is known, the

switching MOSFET conduction losses can be calculated:

PRMS(H) + IRMS(H)2

RDS(ON)

where:

The upper MOSFET switching losses are caused during

MOSFET switch−on and switch−off and can be determined

by using the following formula:

PSWH + PSWH(ON) ) PSWH(OFF)

+

VIN

IOUT

(tRISE ) tFALL)

6T

where:

switching characteristics performance curve);

switching characteristics performance curve);

The total power dissipation in the switching MOSFET can

then be calculated as:

PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)

where:

Once the total power dissipation in the switching FET is

known, the maximum FET switch junction temperature can

be calculated:

TJ + TA ) [PHFET(TOTAL)

RQJA]

where:

Selection of the Synchronous (Lower) FET

The switch conduction losses for the lower FET can be

calculated as follows:

+ [IOUT

(1 * D)]2

RDS(ON)

PRMS(L) + IRMS2

RDS(ON)

where:

D = Duty Cycle;

The synchronous MOSFET has no switching losses,

except for losses in the internal body diode, because it turns

on into near zero voltage conditions. The MOSFET body

diode will conduct during the non−overlap time and the

resulting power dissipation (neglecting reverse recovery

losses) can be calculated as follows:

PSWL + VSD

ILOAD

non−overlap time

fSW

where:

Non−overlap time = GATE(L)−to−GATE(H) or

GATE(H)−to−GATE(L) delay (from CS5422 data sheet

Electrical Characteristics section);

The total power dissipation in the synchronous (lower)

MOSFET can then be calculated as:

PLFET(TOTAL) + PRMS(L) ) PSWL

where:

Once the total power dissipation in the synchronous FET

is known the maximum FET switch junction temperature

can be calculated:

TJ + TA ) [PLFET(TOTAL)

RQJA]

where: