ADM6819/ADM6820

Rev. 0 | Page 10 of 12

THEORY OF OPERATION

The ADM6819/ADM6820 provide local voltage sequencing in

multisupply systems. Figure 18 and Figure 19 show typical

application diagrams for these devices.

Q1

GATE

SETV

EN

GND

R1

R2

ADM6819

ON

OFF

Figure 18. ADM6819 Applications Diagram

Q1

GATE

SETV

SETD

GND

R1

R2

ADM6820

Figure 19. ADM6820 Applications Diagram

When the primary supply is above the desired threshold, the

ADM6819/ADM6820 are designed to control the N-channel

FET in the secondary power path to enable the secondary

below the undervoltage threshold, ensuring that the FET is held

is above the desired level dictated by the resistor divider to the

VSET pin, the external FET is driven on after the delay has

expired. An internal charge pump enhances the external FET. A

chosen to reduce voltage drop across the drain-source when the

FET is fully enhanced. Either supply may act as the primary

is the main supply.

SETV PIN

The ADM6819/ADM6820 enable a supply after a monitored

supply voltage exceeds a programmed threshold. This threshold

is programmed by a R1/R2 resistor divider on the SETV pin.

Once the voltage on SETV exceeds the 0.618 V threshold, the

FET switches on after the delay timer expires. On the

ADM6820, this delay is programmable using a capacitor on the

SETD pin. On the ADM6819, this delay is fixed at 300 ms and

the EN pin must be valid high to begin the timer. The required

turn-on voltage is calculated by the following equation:

where:

VTRIP is the minimum turn-on voltage at the supply being

monitored.

High value resistors can be used because the SETV input

current is typically 10 nA.

EN PIN

The ADM6819 has an enable (EN) pin connected to the input

of a second comparator, which is identical to that on the VSET

below 0.6 V. Alternatively, the enable input can be used to

validate a second supply. The fixed 300 ms timer does not begin

counting until both SETV and EN are above the threshold. As a

result, the output is not enabled until this timer has expired.

GATE PIN

The internal charge pump is capable of driving the gate of an

N-channel MOSFET with no external capacitors. This ensures

that the MOSFET is enhanced to provide a minimum voltage

drop across the MOSFET, thus reducing the voltage drop across

the FET. This charge pump is designed to drive the high imped-

ance capacitive load of a MOSFET gate input. The GATE pin

should not be resistively loaded because it reduces the gate drive

capability. During undervoltage lockout, GATE is held to GND.

SETD PIN

The ADM6820 features a capacitor adjustable sequencing delay.

A capacitor connected to the SETD pin determines the length

of the sequencing delay. The sequencing delay can be calculated

by the following equation:

The ADM6819 has a fixed 300 ms delay.