Nexperia

74LVC138A

3-to-8 line decoder/demultiplexer; inverting

4. Functional diagram

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

7

9

10

11

12

13

14

15

A0

A1

A2

3

2

1

6

5

4

E2

E1

E3

mna370

Fig. 1. Logic symbol

mna371

7

9

10

11

12

13

14

&

X/Y

15

7

EN

6

5

4

3

2

1

0

6

5

4

3

2

1

1

4

2

7

9

10

11

12

13

14

&

DX

(a)

(b)

15

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

2

G 07

Fig. 2. IEC logic symbol

mna372

ENABLE

EXITING

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

7

9

10

11

12

13

14

15

A0

A1

A2

3-to-8

DECODER

3

2

1

6

5

4

E2

E1

E3

Fig. 3. Functional diagram

5. Pinning information

5.1. Pinning

74LVC138A

A0

VCC

A1

Y0

A2

Y1

E1

Y2

E2

Y3

E3

Y4

Y7

Y5

GND

Y6

001aad033

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 4. Pin configuration SOT109-1 (SO16)

74LVC138A

A0

VCC

A1

Y0

A2

Y1

E1

Y2

E2

Y3

E3

Y4

Y7

Y5

GND

Y6

aaa-029538

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration SOT403-1 (TSSOP16)

74LVC138A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 8 — 20 September 2021

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