Nexperia

74LVC157A

Quad 2-input multiplexer

1Y

1I1

1I0

2Y

2I1

2I0

3Y

3I1

3I0

mna484

4Y

4I1

4I0

S

E

Fig. 4. Logic diagram

5. Pinning information

5.1. Pinning

74LVC157A

S

VCC

1I0

E

1I1

4I0

1Y

4I1

2I0

4Y

2I1

3I0

2Y

3I1

GND

3Y

001aac930

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration for SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

001aac931

74LVC157A

2Y

3I1

2I1

3I0

2I0

4Y

GND(1)

1Y

4I1

1I1

4I0

1I0

E

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area

(1) This is not a supply pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 6. Pin configuration for SOT763-1 (DHVQFN16)

74LVC157A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 10 — 20 September 2021

3 / 15