Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

mna362

tPLZ

tPHZ

outputs

disabled

outputs

enabled

VY

VX

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

nOE input

VI

VOL

VOH

VCC

VM

GND

GND

tPZL

tPZH

VM

VM

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 7. 3-state enable and disable times

001aaa257

GND

GND

th

tsu

th

tsu

VM

VM

VM

VI

VOH

VOL

VI

nQn output

nCP input

nDn input

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable performance.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 8. Data set-up and hold times for the nDn input to the nCP input

Table 8. Measurement points

Supply voltage

Input

Output

VCC

VI

VM

VM

VX

VY

1.2 V

VCC

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

1.65 V to 1.95 V

VCC

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

2.3 V to 2.7 V

VCC

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

2.7 V

2.7 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

3.0 V to 3.6 V

2.7 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

74LVC_LVCH16374A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 13 — 27 September 2021

8 / 13