Nexperia

74LVC257A

Quad 2-input multiplexer with 5 V tolerant inputs/outputs; 3-state

5. Pinning information

5.1. Pinning

74LVC257A

S

VCC

1I0

OE

1I1

4I0

1Y

4I1

2I0

4Y

2I1

3I0

2Y

3I1

GND

3Y

001aad097

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

001aad098

74LVC257A

2Y

3I1

2I1

3I0

2I0

4Y

GND(1)

1Y

4I1

1I1

4I0

1I0

OE

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 6. Pin configuration SOT763-1 (DHVQFN16)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

S

1

common data select input

1I0, 2I0, 3I0, 4I0

2, 5, 11, 14

data input from source 0

1I1, 2I1, 3I1, 4I1

3, 6, 10, 13

data input from source 1

1Y, 2Y, 3Y, 4Y

4, 7, 9, 12

3-state multiplexer output

GND

8

ground (0 V)

OE

15

3-state output enable input (active LOW)

VCC

16

supply voltage

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state

Input

Output

OE

S

nI0

nI1

nY

H

X

X

X

Z

L

H

X

L

L

L

H

X

H

H

L

L

L

X

L

L

L

H

X

H

74LVC257A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 8 — 31 August 2021

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