Nexperia

74LVC273

Octal D-type flip-flop with reset; positive-edge trigger

mna464

MR input

CP input

Qn output

tPHL

tW

trec

VM

VI

GND

VI

VOL

GND

VM

VM

VOH

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 6. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays, and the master reset to

clock (CP) recovery time

mna767

GND

GND

th

tsu

th

tsu

VM

VM

VM

VI

VOH

VOL

VI

Qn output

CP input

Dn input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 7. Data set-up and hold times for the data input (Dn)

Table 8. Measurement points

Supply voltage

Input

Output

VCC

VI

VM

VM

VX

VY

1.2 V

VCC

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

1.65 V to 1.95 V

VCC

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

2.3 V to 2.7 V

VCC

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

2.7 V

2.7 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

3.0 V to 3.6 V

2.7 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

74LVC273

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 8 — 31 August 2021

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