Nexperia

74LVC377

Octal D-type flip-flop with data enable; positive-edge trigger

4. Functional diagram

mna918

D0

D1

D2

D3

D4

D5

D6

D7

E

CP

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

11

1

19

16

15

12

9

6

5

2

18

17

14

13

8

7

4

3

Fig. 1. Logic symbol

mna919

19

16

15

12

9

6

5

11

1C2

1

G1

2D

2

18

17

14

13

8

7

4

3

Fig. 2. IEC logic symbol

5. Pinning information

5.1. Pinning

74LVC377

E

VCC

Q0

Q7

D0

D7

D1

D6

Q1

Q6

Q2

Q5

D2

D5

D3

D4

Q3

Q4

GND

CP

mna917

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

Fig. 3. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

E

1

data enable input (active LOW)

CP

11

clock input (LOW to HIGH; edge-triggered)

D0, D1, D2, D3, D4, D5, D6, D7

3, 4, 7, 8, 13, 14, 17, 18

data input

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

2, 5, 6, 9, 12, 15, 16, 19

flip-flop output

GND

10

ground (0 V)

VCC

20

power supply

74LVC377

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Product data sheet

Rev. 7 — 27 August 2021

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