Nexperia

74LVC574A

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

6. Functional description

Table 3. Functional table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition;

↑ = LOW to HIGH clock transition;

Z = high-impedance OFF-state

Input

Output

Operating modes

OE

CP

Dn

Internal

flip-flop

Qn

L

↑

l

L

L

Load and read register

L

↑

h

H

H

H

↑

l

L

Z

Load register and disable outputs

H

↑

h

H

Z

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

-0.5

+6.5

V

IIK

input clamping current

VI < 0

-50

-

mA

VI

input voltage

[1]

-0.5

+6.5

V

IOK

output clamping current

VO > VCC or VO < 0

-

±50

mA

VO

output voltage

output HIGH or LOW state

[2]

-0.5

VCC + 0.5

V

IO

output current

VO = 0 V to VCC

-

±50

mA

ICC

supply current

-

100

mA

IGND

ground current

-100

-

mA

Tstg

storage temperature

-65

+150

°C

Ptot

total power dissipation

Tamb = -40 °C to +125 °C

[3]

-

500

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C.

For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C.

For SOT764-1 (DHVQFN20) package: Ptot derates linearly with 12.9 mW/K above 111 °C.

74LVC574A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 30 August 2021

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