Nexperia

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

6. Pinning information

6.1. Pinning

74LVC595A

Q1

VCC

Q2

Q0

Q3

DS

Q4

OE

Q5

STCP

Q6

SHCP

Q7

MR

GND

Q7S

001aaf569

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

001aaf570

74LVC595A

Q7

MR

Q6

SHCP

Q5

STCP

Q4

OE

Q3

DS

Q2

Q0

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 6. Pin configuration SOT763-1 (DHVQFN16)

6.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

15, 1, 2, 3, 4, 5, 6, 7

parallel data output

GND

8

ground (0 V)

Q7S

9

serial data output

MR

10

master reset (active LOW)

SHCP

11

shift register clock input

STCP

12

storage register clock input

OE

13

output enable input (active LOW)

DS

14

serial data input

VCC

16

supply voltage

74LVC595A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 3 — 19 November 2021

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