Nexperia

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

mna561

MR input

SHCP input

Q7S output

tPHL

tW

trec

VM

VOH

VOL

VI

GND

VI

GND

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig. 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and

the master reset to shift clock (SHCP) recovery time

001aae821

tPLZ

tPHZ

outputs

disabled

outputs

enabled

VY

VX

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VI

VCC

VM

VOL

VOH

GND

GND

tPZL

tPZH

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig. 12. 3-state enable and disable times

Table 8. Measurement points

Supply voltage

Input

Output

VCC

VM

VM

VX

VY

VCC < 2.7 V

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

VCC ≥ 2.7 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

74LVC595A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 3 — 19 November 2021

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