ADP1621ARMZ-R7 datasheet(20/32 Pages) AD

20 / 32 page

ADP1621

Rev. A | Page 20 of 32

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators, but is par-

ticularly important for regulators with high switching frequencies.

To achieve high efficiency, good regulation, and stability, a well-

designed printed circuit board layout is required. A sample PCB

layout for the standard boost converter circuit shown in Figure 33

is given in Figure 32.

Follow these guidelines when designing printed circuit boards:

•

Keep the low ESR bypass input capacitor of 0.1 μF or higher

close to IN/PIN and GND.

•

Keep the high current path from Bulk Input Capacitor C1

through Inductor L1 and MOSFET M1 to PGND as short

as possible.

•

Keep the high current path from Bulk Input Capacitor C1

through Inductor L1, Diode D1, and Output Capacitor COUT

to PGND as short as possible. Place COUT as close to PGND

as possible to reduce ground bouncing.

•

Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and electromagnetic interference (EMI).

•

To minimize switching noise, the drain of the power MOSFET

should be placed very close to the inductor, and the source

of the MOSFET (or the bottom side of the sense resistor)

should be connected directly to the power GND plane. Use

wide copper traces on the drain and on the source of the

MOSFET to minimize parasitic inductance and resistance.

Parasitic inductance can lead to excessive ringing during

switching transitions, and parasitic resistance reduces the

converter efficiency. Make sure that the MOSFET selected

is capable of handling the total power loss (conduction plus

transition losses) in the application circuit.

•

Avoid routing high impedance traces near any node con-

nected to the switch node (the MOSFET drain) or near

Inductor L1 to prevent radiated switching-noise injection.

•

Add an extra copper plane at the connection of the MOSFET

drain and the anode of the diode to help dissipate the heat

generated by losses in those components.

•

Avoid ground loops by having one central ground node on the

PCB. If this is impractical, place the power ground with high

current levels physically closer to the PCB ground terminal.

The analog, low current-level ground should be placed farther

from the PCB ground terminal.

•

Minimize the length of the PCB trace between the GATE

pin and the MOSFET gate. The parasitic inductance in this

PCB trace can give rise to excessive voltage ringing at the

MOSFET gate and drain, as well as the regulator output. It

is recommended to add 5 Ω of resistance for every inch of

PCB trace. This helps to reduce the overshoot and ringing at

the drain and the output. However, this added resistance

increases the rise and fall times of the MOSFET; thus, the

switching loss in the MOSFET is increased.

•

Place the feedback resistors as close to FB as possible to

prevent high frequency switching-noise injection.

•

Place the top of the upper feedback resistor, R1, as close

as possible to the top of COUT for optimum output voltage

sensing.

•

If a current-sense resistor is connected between the source

of the MOSFET and PGND, ensure that the capacitance from

CS to PGND is minimized.

•

Place the compensation components as close as possible

to COMP.

VIN

VOUT

COUT1

COUT2

VIAS TO GND PLANE

VIAS TO 2ND LAYER

REMOTE OUTPUT

SENSING

COUT3

GND

SDSN

ADP1621

RFREQ

GATE

Figure 32. PCB Layout of the Circuit Shown in Figure 33 (2-layer PCB)

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