MC68340 datasheet(39/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

2- 5

last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus

are driven, regardless of the port width or operand size. The MC68340 places the data on

the data bus approximately one-half clock cycle after

AS is asserted in a write cycle.

2.4 FUNCTION CODES (FC3–FC0)

These signals are outputs that indicate one of 16 address spaces to which the address

applies. Fifteen of these spaces are designated as either user or supervisor, program or

data, and normal or direct memory access (DMA) spaces. One other address space is

designated as CPU space to allow the CPU32 to acquire specific control information not

normally associated with read or write bus cycles. The function code signals are valid

while

AS is asserted. See Table 2-2 for more information.

Table 2-2. Address Space Encoding

Function Code Bits

3210

Address Spaces

0000

Reserved (Motorola)

0001

User Data Space

0010

User Program Space

0011

Reserved (User )

0100

Reserved (Motorola)

0101

Supervisor Data Space

0110

Supervisor Program Space

0111

CPU Space

DMA Space

2.5 CHIP SELECTS

(CS3–CS0)

These pins can be programmed to be chip select output signals, port B parallel I/O and

autovector input, or additional interrupt request lines. Refer to Section 4 System

Integration Module for more information on these signals.

CS3– CS0

The chip select output signals enable peripherals at programmed addresses. These

signals are inactive high (not high impedance) after reset.

CS0 is the chip select for a

boot ROM containing the reset vector and initialization program. It functions as the boot

chip select immediately after reset.

IRQ4, IRQ2, IRQ1

Interrupt request lines are external interrupt lines to the CPU32. These additional

interrupt request lines are selected by the FIRQ bit in the module configuration register.

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