Nexperia

74LVC08A

Quad 2-input AND gate

4. Functional diagram

mna222

1A

1B

1Y

2

1

3

2A

2B

2Y

5

4

6

3A

3B

3Y

10

9

8

4A

4B

4Y

13

12

11

Fig. 1. Logic symbol

mna223

3

&

&

&

&

2

1

6

5

4

8

10

9

11

13

12

Fig. 2. IEC logic symbol

mna221

A

B

Y

Fig. 3. Logic diagram for one gate

5. Pinning information

5.1. Pinning

74LVC08A

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

001aac945

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aac946

74LVC08A

GND(1)

Transparent top view

2Y

3A

2B

3B

2A

4Y

1Y

4A

1B

4B

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1A, 2A, 3A, 4A

1, 4, 9, 12

data input

1B, 2B, 3B, 4B

2, 5, 10, 13

data input

1Y, 2Y, 3Y, 4Y

3, 6, 8, 11

data output

GND

7

ground (0 V)

VCC

14

supply voltage

74LVC08A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 9 — 17 September 2021

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