Nexperia

74LVC2G34

Dual buffer gate

6. Pinning information

6.1. Pinning

74LVC2G34

1A

1Y

GND

2A

2Y

001aab676

1

2

3

6

VCC

5

4

Fig. 4. Pin configuration SOT363-2 (TSSOP6) and

SOT457 (SC-74; TSOP6)

74LVC2G34

GND

001aab677

1A

2A

VCC

1Y

2Y

Transparent top view

2

3

1

5

4

6

Fig. 5. Pin configuration SOT886 (XSON6)

74LVC2G34

GND

001aag030

1A

2A

VCC

1Y

2Y

Transparent top view

2

3

1

5

4

6

Fig. 6. Pin configuration SOT1115 and

SOT1202 (XSON6)

2

5

4

3

6

1

2A

1A

2Y

GND

VCC

1Y

74LVC2G34

aaa-021911

Transparent top view

Fig. 7. Pin configuration SOT1255-2 (X2SON6)

6.2. Pin description

Table 3. Pin description

Symbol

Pin

Description

1A

1

data input

GND

2

ground (0 V)

2A

3

data input

2Y

4

data output

VCC

5

supply voltage

1Y

6

data output

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level.

Input

Output

nA

nY

L

L

H

H

74LVC2G34

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Product data sheet

Rev. 12 — 20 January 2022

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