Nexperia

74LVC2G38

Dual 2-input NAND gate; open drain

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1B

2B

1A

2Y

1Y

2A

Transparent top view

3

6

1

5

7

2

terminal 1

index area

74LVC2G38

Fig. 6. Pin configuration SOT902-2 (XQFN8)

8

4

VCC

GND

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Transparent top view

74LVC2G38

1

2

3

1A

1B

2Y

7

6

5

1Y

2B

2A

Fig. 7. Pin configuration SOT1233-2 (X2SON8)

6.2. Pin description

Table 3. Pin description

Pin

Symbol

SOT505-2, SOT765-1, SOT833-1, SOT1089,

SOT1116, SOT1203 and SOT1233-2

SOT902-2

Description

1A, 2A

1, 5

7, 3

data input

1B, 2B

2, 6

6, 2

data input

GND

4

4

ground (0 V)

1Y, 2Y

7, 3

1, 5

data output

VCC

8

8

supply voltage

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

Input

Output

nA

nB

nY

L

L

Z

L

H

Z

H

L

Z

H

H

L

74LVC2G38

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Product data sheet

Rev. 14 — 21 June 2022

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