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74LVC2G74DP 数据表(PDF) 9 Page - Nexperia B.V. All rights reserved |
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74LVC2G74DP 数据表(HTML) 9 Page - Nexperia B.V. All rights reserved |
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9 / 18 page ![]() Nexperia 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger mnb142 trec tPHL tPHL tW tPLH tPLH VM VM VM tW VM VM VI GND VI GND SD input VI GND RD input CP input VOH VOL Q output VOH VOL Q output trec Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP recovery time Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC 74LVC2G74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 14 — 27 August 2021 9 / 18 |
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