Nexperia

74LVC2T45; 74LVCH2T45

Dual supply translating transceiver; 3-state

13.2. Bidirectional logic level-shifting application

Fig. 15 shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic level-shifting

application. Since the device does not have an output enable pin, the system designer should take

precautions to avoid bus contention between system-1 and system-2 when changing directions.

001aai932

PULL-UP/DOWN

system-1

VCC(A)

1A

2A

GND

1

2

3

4

8

7

6

5

VCC(B)

1B

2B

DIR

74LVC2T45

74LVCH2T45

PULL-UP/DOWN

I/O-1

DIR CTRL

VCC1

I/O-2

DIR CTRL

VCC2

VCC1

VCC2

system-2

Pull-up or pull-down only needed for 74LVC2T45.

Fig. 15. Bidirectional logic level-shifting application

Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then

from system-2 to system-1.

Table 17. Description of bidirectional logic level-shifting application

H = HIGH voltage level;

L = LOW voltage level;

Z = high-impedance OFF-state.

State

DIR CTRL I/O-1

I/O-2

Description

1

H

output

input

system-1 data to system-2

2

H

Z

Z

system-2 is getting ready to send data to

system-1. I/O-1 and I/O-2 are disabled.

The bus-line state depends on bus hold

3

L

Z

Z

DIR bit is set LOW.

I/O-1 and I/O-2 still are disabled.

The bus-line state depends on bus hold

4

L

input

output

system-2 data to system-1

13.3. Power-up considerations

The device is designed such that no special power-up sequence is required other than GND being

applied first.

Table 18. Typical total supply current (ICC(A) + ICC(B))

VCC(B)

VCC(A)

0 V

1.8 V

2.5 V

3.3 V

5.0 V

Unit

0 V

0

< 1

< 1

< 1

< 1

μA

1.8 V

< 1

< 2

< 2

< 2

2

μA

2.5 V

< 1

< 2

< 2

< 2

< 2

μA

3.3 V

< 1

< 2

< 2

< 2

< 2

μA

5.0 V

< 1

2

< 2

< 2

< 2

μA

74LVC_LVCH2T45

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2023. All rights reserved

Product data sheet

Rev. 12 — 1 March 2023

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